This presentation shows the SCADE System product line for systems modeling and generation based on the SysML standard and the Eclipse Papyrus open source technology. SCADE System has been developed in the framework of Listerel, a joint laboratory of Esterel Technologies, provider of the SCADE�, and CEA LIST, project leader of the Eclipse component, Papyrus. From an architecture point of view, the Esterel SCADE tools are built on top of the SCADE platform which includes both SCADE Suite�, a model-based development environment dedicated to critical software, and SCADE System enabling model-based system engineering. SCADE System includes Papyrus, an open source component (under EPL license), integrated in the modeling platform of Eclipse. Using this integrated modeling platform, both system and software teams share the same environment for system development. Furthermore, other model-based tools can be added to the environment, due to the use of Eclipse.
The Correlation of As-Manufactured Products to As-Designed Specifications: Closing the Loop on Dimensional Quality Results to Engineering Predictions
Simulation-based tolerance analysis is the accepted standard for dimensional engineering in aerospace today. Sophisticated 3D model-based tolerance analysis processes enable engineers to measure variation in complex, often large, assembled products quickly and accurately. Best-in-class manufacturers have adopted Quality Intelligence Management tools for collecting and consolidating this measurement data. Their goal is to completely understand dimensional fit characteristics and quality status before commencing the build process. This results in shorter launch cycles, improved process capabilities, reduced scrap and less production downtime. This paper describes how to use simulation-based approaches to correlate the theoretical tolerance analysis results produced during engineering simulations to actual as-built results. This allows engineers to validate or adjust as-designed simulation parameters to more closely align to production process capabilities.
Given the fast changing market demands, the growing complexity of features, the shorter time to market, and the design/development constraints, the need for efficient and effective verification and validation methods are becoming critical for vehicle manufacturers and suppliers. One such example is fault-tree analysis. While fault-tree analysis is an important hazard analysis/verification activity, the current process of translating design details (e.g., system level and software level) is manual. Current experience indicates that fault tree analysis involves both creative deductive thinking and more mechanical steps, which typically involve instantiating gates and events in fault trees following fixed patterns. Specifically for software fault tree analysis, a number of the development steps typically involve instantiating fixed patterns of gates and events based upon the structure of the code. In this work, we investigate a methodology to translate software programs to fault trees.